XILINX

FPGA Design Training

What is the Difference Between an FPGA and an ASIC - Part 1

Learn how to describe the differences between ASIC and FPGA architectures, explain the features of Xilinx FPGA architecture, realize the benefit from Xilinx dedicated resources. More
Released: Jan 2009Views: 634

What is the Difference Between an FPGA and an ASIC - Part 2

Learn how to describe how a simple logic implementation can differ between ASIC and FPGAs, recognize gate counts as an estimation of design size and explain some of the FPGA design practices to obtain maximum performance in your FPGA. More
Released: Jan 2009Views: 175

FPGA vs. ASIC Design Flow

Learn how to desribe the differences between ASIC and FPGA Design flows including: design methodology, verification techniques, test-generation logic and tools. More
Released: Jan 2009Views: 352

How to Convert ASIC Code to FPGA Code - Part 1

Learn how to optimize ASIC code for implementation in an FPGA and describe the steps to perform ASIC to FPGA code conversion. More
Released: Jan 2009Views: 180

How to Convert ASIC Code to FPGA Code - Part 2

Learn how to optimize code implementation in an FPGA and describe the steps to perform ASIC to FPGA code conversion. More
Released: Jan 2009Views: 96

How to Configure an FPGA - Part 1

Learn how to describe the FPGA configuration pins, choose an appropriate FPGA configuration scheme, connect multiple FPGAs into a configuration daisy chain, and describe currently available prototyping hardware. More
Updated: Sept 2009Views: 5,856

How to Configure an FPGA - Part 2

Learn how to describe the FPGA configuration pins, choose an appropriate FPGA configuration scheme, connect multiple FPGAs into a configuration daisy chain, and describe currently available prototyping hardware. More
Updated: Sept 2009Views: 1,784

Architecture Wizard and I/O Planning

Learn how to list at least two uses for the Architecture Wizard, identify two features of PinAhead, and create quality pin assignments for Xilinx FPGAs. More
Updated: Sept 2009Views: 3,230

   Virtex-6 Memory Resources

Learn how to fully utilize the Virtex®-6 distributed memory, block memory, and FIFO resources, use the Memory Interface Generator (MIG) to build a custom memory controller for your off-chip memory component. More
Released: Oct 2009Views: 2,200

   Virtex-6 Slice and I/O Resources

Learn how to describe the basic slice and I/O resources available in Virtex-6 FPGAs. More
Released: Oct 2009Views: 3,443

   Virtex-6 Clocking Resources

Learn how to detail the clocking resources available in the Virtex-6 FPGA, specify the resources available in the Clock Management Tile (CMT), describe the basics of the PLL capabilities. More
Released: Oct 2009Views: 2,408

   Spartan-6 Memory Resources

Learn how to fully utilize the Spartan®-6 distributed and block memory resources, understand the features and limitations of the Spartan-6 dedicated memory controller block (MCB), use the Memory Interface Generator (MIG) to build your custom memory controller and design an appropriate interface to your off-chip memory component. More
Released: Oct 2009Views: 2,106

   Spartan-6 Slice and I/O Resources

Learn how to describe the basic slice and I/O resources available in Spartan-6 FPGAs. More
Released: Oct 2009Views: 3,539

   Spartan-6 Clocking Resources

Learn how to describe the global and I/O clock networks in the Spartan-6 FPGA, describe the clock buffers and their relationships to the I/O resources, describe the DCM capabilities in the Spartan-6 FPGA. More
Released: Oct 2009Views: 2,456

Spartan-3E FPGA Architecture Overview

Learn how to describe how the architecture of the Spartan®-3E FPGA differs from the architecture of the Spartan-3 FPGA, determine if the Spartan-3E FPGA architecture fits your application requirements, and describe the new features of the Spartan-3E FPGA platform. More
Released: Aug 2005Views: 696

Spartan-3 FPGA Architecture Overview

Learn how to describe the Spartan-3 architecture, its underlying technology and target markets, as well as its design entry, implementation, and verification software support features. You will also know how to describe the system solutions for DSP, MicroBlaze™ embedded processor, and communications connectivity. More
Released: Aug 2005Views: 824

Achieving Breakthrough Performance in Virtex-4 FPGAs

Learn how to describe Virtex-4 FPGA advantages, discuss how to achieve optimum FPGA performance, and describe the Virtex-4 FPGA performance comparison methodology. More
Released: Aug 2005Views: 177

Clocking Techniques for Virtex-II FPGAs

Learn how to describe the features and limitations of the DCM, BUFGMUX, and global routing resources, and explain how to build a clock assignment strategy for your design. More
Released: Aug 2005Views: 215

ChipScope Pro Software Overview

Learn how to describe the value of the ChipScope™ Pro software, describe how it works, list available relevant cores, use the Core Generator and Core Inserter software, plan for debug, and debug with the ChipScope Pro software. Links to the labs are at the end of the recording. More
Updated: Oct 2009Views: 2,044

   Global Timing Constraints

Learn how to apply global timing constraints to a simple synchronous design, use the Xilinx Constraints Editor to specify global timing constraints. More
Released: Oct 2009Views: 282

Area Constraints

Learn how to make an effective layout with area constraints, use area constraints to improve the speed of your design by grouping critical paths, use area constraints to localize (and maximize) your designs clocks, and use area constraints in an incremental design flow. More
Released: Aug 2005Views: 546

Timing Closure Flow

Learn how to describe the overall flow for achieving timing closure, specify the key elements in achieving timing closure, describe the importance of cores and coding for performance, list some of the key implementation options in timing closure, and state where to learn more about each step in the timing closure flow. More
Released: Aug 2005Views: 926

DDR-I SDRAM Memory Interface

Learn how to list the Virtex-II and Virtex-II Pro device features that enable high-speed memory interface design, calculate timing margins for the Virtex-II series DDR-I interface design, and access memory resources on the Xilinx website, including the Xilinx Memory Tool Kit. More
Released: Aug 2005Views: 336

SPI-4.2 Overview

Learn how to identify the basics of the OSI 7 Layer Model, describe the protocol, specifications, and competitive advantages of the SPI-4.2 solution, and explain how the SPI-4.2 solution fits into the OSI 7 Layer Model. More
Released: Aug 2005Views: 241

IC Packaging Overview

Learn how to describe the correct IC package to meet your design goals, list the various sources of heat generation in IC packages, identify and defines critical thermal variables, discuss Xilinx-provided specs to manage your thermal budget. More
Released: Aug 2005Views: 188

Power Estimation

Learn how to list the three phases of the design cycle where power calculations can be performed, estimate power consumption by using the XPower Estimator spreadsheet, estimate power consumption by using the XPower software utility. More
Released: Sept 2009Views: 104

Synthesis Options

Learn how to identify synthesis tool options that can be used to increase performance and/or reduce your design size, describe an approach to using your synthesis tool to obtain higher performance and gain timing closure, use XST to get the most out of your HDL. More
Released: Sept 2009Views: 180

Core Generator Software System

Learn how to describe the differences between LogiCORE™ and AllianceCORE solutions, identify two benefits of using cores in your designs, create customized cores by using the CORE Generator software system GUI, instantiate cores into your HDL design, run behavioral simulation on a design that contains cores. More
Released: Nov 2009Views: 80

Embedded Design Training

   Embedded Design with the Xilinx Embedded Developer Kit

If you are new to Embedded design with Xilinx FPGAs, this training will help you: start planning your design, understand the difference between Xilinx’s FPGA architectures is essential if you are going to select an appropriate FPGA device family. After completing this training you will know how to: decidingly choose between a PowerPC® 440 and a MicroBlaze™ processor system, explain the primary tool functionality included with the Embedded Development Kit, explain the benefits of building an embedded design with an FPGA More
Released: Feb 2010Views: NEW!

   Embedded Design with the MicorBlaze Soft Processor Core

If you are new to Embedded design with Xilinx FPGA's, this module will explain why you may want to use the MicroBlaze soft processor core in any of our FPGA families. It will aid in your understanding of MicroBlaze basics which will enable you to take full advantage of its features. After completing this training you will know how to explain how the utilities included with the Embedded Developers Kit (EDK) are optimized for MicroBlaze and explain how the Base System Builder makes it easy to build your embedded system. More
Released: Feb 2010Views: NEW!

   Embedded Design with the PPC 440 Processor Core

If you are new to Embedded design with Xilinx FPGA’s, this module will explain why you may want to use the PowerPC 440 processor in the Virtex-5 FX FPGA family. After completing this training you will know how to: explain some of the benefits of the PPC 440 processor, explain how the utilities included with the Embedded Developers Kit (EDK) are optimized for the PPC 440 processor and explain how the Base System Builder makes it easy to make your embedded system. More
Released: Feb 2010Views: NEW!

Connectivity Design Training

PCI Express Overview

Learn how to explain the background behind PCI Express®, identify the differences between PCI and PCI Express, and describe a basic PCI Express Link, the different layers of a PCI Express device, and the Xilinx PCI Express solution. More
Released: Jan 2005Views: 721

DSP Design Training

Getting Started with System Generator

Learn how to create a DSP design that includes memories and control using Simulink and implement that design into a Xilinx FPGA, design highly efficient FIR filters for Xilinx device architectures, and define fixed-point numeric precision abstractly using the Xilinx DSP blockset. More
Released: Oct 2006Views: 1,963

AccelDSP Jump Start Training

Learn how to modify a MATLAB® script for a DSP algorithm for synthesis using the AccelDSP Synthesis Tool, identify the concepts of quantization as well as specify, monitor, and control bit growth in a MATLAB design, and apply MATLAB coding style changes and AccelDSP directives to optimize a design for performance and efficiency. More
Released: Sept 2006Views: 993

CPLD Design Training

CoolRunner-II CPLD: Clocking and I/O

Learn how to describe the clock divider and DualEDGE features of CoolRunner™-II CPLDs, list applications that can benefit from these clocking features, and describe several solutions for special signaling and interface requirements. More
Released: Oct 2005Views: 335

Programming Language Training

   Virtex-6 & Spartan-6 FPGA HDL Coding Techniques - Part 1

Learn how to code your register resources so your design will have fewer control sets and run at a higher system speed, avoid the most common coding mistakes that reduce device utilization and system speed, anticipate how your design will map to the register resources. More
Released: Sept 2009Views: 285

   Virtex-6 & Spartan-6 FPGA HDL Coding Techniques - Part 2

Learn how to code your design so you can infer more of the dedicated hardware resources, avoid the most common coding mistakes which hurt device utilization, reduce your dependence on global resets by taking advantage of the Global Set/Reset net (GSR). More
Released: Sept 2009Views: 126

Virtex-5 FPGA HDL Coding Techniques - Part 1

Learn how to code properly for Virtex-5 FPGA register resources. You will also know how to manage your control signal usage so that you can build a smaller FPGA design that will run at the highest system speed possible. More
Released: Sept 2009Views: 731

Virtex-5 FPGA HDL Coding Techniques - Part 2

Learn how to code properly for 6-input LUT and block RAM resources in the Virtex-5 FPGA. You will also know how to manage your control signal usage so that you can build a high-speed FPGA design. Finally, you will identify the most important considerations for migrating an existing design to the Virtex-5 FPGA. More
Released: Sept 2009Views: 354

Spartan-3 FPGA HDL Coding Techniques - Part 1

Learn how to code properly for FPGA registers, SRLs, and other dedicated resources. These techniques will enable you to build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs. More
Released: Sept 2009Views: 1,073

Spartan-3 FPGA HDL Coding Techniques - Part 2

Learn how to code properly for carry logic and memory resources. You will also know how to manage your control signal usage so that you can build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs. More
Released: Sept 2009Views: 404

Basic HDL Coding Techniques - Part 1

Learn how to describe primary coding techniques for FPGAs, including basic design guidelines that successful FPGA designers follow and explain proper coding techniques for combinatorial and registered logic. More
Released: Sept 2009Views: 3,617

Basic HDL Coding Techniques - Part 2

Learn how to describe primary coding techniques for FPGAs, including basic design guidelines that successful FPGA designers follow, as well as, Finite State Machine design and building pipeline stages. More
Released: Sept 2009Views: 1,096

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